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authorGeorgiy Samoylov <g.samoylov@syntacore.com>2025-09-12 11:49:33 +0300
committerGitHub <noreply@github.com>2025-09-12 11:49:33 +0300
commitfae68b6c77058dd10d7c6780181ff312e46f0689 (patch)
treea37b60e37d01530bbf612ee87c1079289b45d67a /llvm/lib/CodeGen/MachineInstr.cpp
parent1b05212acc1964837135930a129ee26e1a392278 (diff)
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[RISCV] Enabled debug entry support by default (#157703)
This patch enables support for debug entry values. This improves quality of debug info for RISC-V
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