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author | Chris Lattner <sabre@nondot.org> | 2006-05-04 01:26:39 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 01:26:39 +0000 |
commit | ee64b6b40fd01eb37ae8225b5bc342b79846b245 (patch) | |
tree | 2d330eb38aeab43085bda6c8067eb2ff2e8fe448 /llvm/lib/CodeGen/MachineInstr.cpp | |
parent | 940cc978ef23d2f3e35904a6ebd9bd456b00f963 (diff) | |
download | llvm-ee64b6b40fd01eb37ae8225b5bc342b79846b245.zip llvm-ee64b6b40fd01eb37ae8225b5bc342b79846b245.tar.gz llvm-ee64b6b40fd01eb37ae8225b5bc342b79846b245.tar.bz2 |
Remove a bunch more dead V9 specific stuff
llvm-svn: 28094
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 27 |
1 files changed, 2 insertions, 25 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 367631c..e300993 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -36,15 +36,6 @@ namespace llvm { extern const TargetInstrDescriptor *TargetInstrDescriptors; } -// Constructor for instructions with variable #operands -MachineInstr::MachineInstr(short opcode, unsigned numOperands) - : Opcode(opcode), - operands(numOperands, MachineOperand()), - parent(0) { - // Make sure that we get added to a machine basicblock - LeakDetector::addGarbageObject(this); -} - /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, /// not a resize for them. It is expected that if you use this that you call /// add* methods below to fill up the operands, instead of the Set methods. @@ -178,14 +169,7 @@ static void print(const MachineOperand &MO, std::ostream &OS, switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (MO.getVRegValue()) { - OS << "%reg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) - OS << "=="; - } - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg(), MRI); + OutputReg(OS, MO.getReg(), MRI); break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); @@ -285,14 +269,7 @@ std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) { std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_VirtualRegister: - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg()); - - if (MO.getVRegValue()) { - if (MO.hasAllocatedReg()) OS << "=="; - OS << "%vreg"; - OutputValue(OS, MO.getVRegValue()); - } + OutputReg(OS, MO.getReg()); break; case MachineOperand::MO_SignExtendedImmed: OS << (long)MO.getImmedValue(); |