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author | Stephen Tozer <Stephen.Tozer@Sony.com> | 2022-09-15 11:26:57 +0100 |
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committer | Stephen Tozer <Stephen.Tozer@Sony.com> | 2023-01-06 18:03:48 +0000 |
commit | e10e936315410abd222eb58911b1e20fbfa80baf (patch) | |
tree | a30eec4a4b1e7413b842c0323a461e3a1b791ba4 /llvm/lib/CodeGen/MachineInstr.cpp | |
parent | bdf7da280f624c53e6184d0410041220a9b405a7 (diff) | |
download | llvm-e10e936315410abd222eb58911b1e20fbfa80baf.zip llvm-e10e936315410abd222eb58911b1e20fbfa80baf.tar.gz llvm-e10e936315410abd222eb58911b1e20fbfa80baf.tar.bz2 |
[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:
* The introduction of a new MachineOperand type, MO_DbgInstrRef, which
consists of two unsigned numbers that are used to index an instruction
and an output operand within that instruction, having a meaning
identical to first two operands of the current DBG_INSTR_REF
instruction. This operand is only used in DBG_INSTR_REF (see below).
* A change in syntax for the DBG_INSTR_REF instruction, shuffling the
operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
and replacing the first two operands with a single MO_DbgInstrRef-type
operand.
This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D129372
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 83 |
1 files changed, 35 insertions, 48 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 1145243..a54618c 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -675,7 +675,7 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other, } bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const { - if (!isDebugValue() || !Other.isDebugValue()) + if (!isDebugValueLike() || !Other.isDebugValueLike()) return false; if (getDebugLoc() != Other.getDebugLoc()) return false; @@ -854,14 +854,14 @@ const DILabel *MachineInstr::getDebugLabel() const { } const MachineOperand &MachineInstr::getDebugVariableOp() const { - assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*"); - unsigned VariableOp = isDebugValueList() ? 0 : 2; + assert((isDebugValueLike()) && "not a DBG_VALUE*"); + unsigned VariableOp = isNonListDebugValue() ? 2 : 0; return getOperand(VariableOp); } MachineOperand &MachineInstr::getDebugVariableOp() { - assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*"); - unsigned VariableOp = isDebugValueList() ? 0 : 2; + assert((isDebugValueLike()) && "not a DBG_VALUE*"); + unsigned VariableOp = isNonListDebugValue() ? 2 : 0; return getOperand(VariableOp); } @@ -870,14 +870,14 @@ const DILocalVariable *MachineInstr::getDebugVariable() const { } const MachineOperand &MachineInstr::getDebugExpressionOp() const { - assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*"); - unsigned ExpressionOp = isDebugValueList() ? 1 : 3; + assert((isDebugValueLike()) && "not a DBG_VALUE*"); + unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1; return getOperand(ExpressionOp); } MachineOperand &MachineInstr::getDebugExpressionOp() { - assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*"); - unsigned ExpressionOp = isDebugValueList() ? 1 : 3; + assert((isDebugValueLike()) && "not a DBG_VALUE*"); + unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1; return getOperand(ExpressionOp); } @@ -2138,41 +2138,35 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID, bool IsIndirect, - const MachineOperand &MO, + ArrayRef<MachineOperand> DebugOps, const MDNode *Variable, const MDNode *Expr) { assert(isa<DILocalVariable>(Variable) && "not a variable"); assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"); - if (MO.isReg()) - return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr); - - auto MIB = BuildMI(MF, DL, MCID).add(MO); - if (IsIndirect) - MIB.addImm(0U); - else - MIB.addReg(0U); - return MIB.addMetadata(Variable).addMetadata(Expr); -} - -MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, - const MCInstrDesc &MCID, bool IsIndirect, - ArrayRef<MachineOperand> MOs, - const MDNode *Variable, const MDNode *Expr) { - assert(isa<DILocalVariable>(Variable) && "not a variable"); - assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); - assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && - "Expected inlined-at fields to agree"); - if (MCID.Opcode == TargetOpcode::DBG_VALUE) - return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr); + if (MCID.Opcode == TargetOpcode::DBG_VALUE) { + assert(DebugOps.size() == 1 && + "DBG_VALUE must contain exactly one debug operand"); + MachineOperand DebugOp = DebugOps[0]; + if (DebugOp.isReg()) + return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable, + Expr); + + auto MIB = BuildMI(MF, DL, MCID).add(DebugOp); + if (IsIndirect) + MIB.addImm(0U); + else + MIB.addReg(0U); + return MIB.addMetadata(Variable).addMetadata(Expr); + } auto MIB = BuildMI(MF, DL, MCID); MIB.addMetadata(Variable).addMetadata(Expr); - for (const MachineOperand &MO : MOs) - if (MO.isReg()) - MIB.addReg(MO.getReg()); + for (const MachineOperand &DebugOp : DebugOps) + if (DebugOp.isReg()) + MIB.addReg(DebugOp.getReg()); else - MIB.add(MO); + MIB.add(DebugOp); return MIB; } @@ -2190,21 +2184,12 @@ MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const DebugLoc &DL, const MCInstrDesc &MCID, - bool IsIndirect, MachineOperand &MO, - const MDNode *Variable, const MDNode *Expr) { - MachineFunction &MF = *BB.getParent(); - MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr); - BB.insert(I, MI); - return MachineInstrBuilder(MF, *MI); -} - -MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, - MachineBasicBlock::iterator I, - const DebugLoc &DL, const MCInstrDesc &MCID, - bool IsIndirect, ArrayRef<MachineOperand> MOs, + bool IsIndirect, + ArrayRef<MachineOperand> DebugOps, const MDNode *Variable, const MDNode *Expr) { MachineFunction &MF = *BB.getParent(); - MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr); + MachineInstr *MI = + BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr); BB.insert(I, MI); return MachineInstrBuilder(MF, *MI); } @@ -2246,6 +2231,8 @@ MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg) { + assert(!Orig.isDebugRef() && + "DBG_INSTR_REF should not reference a virtual register."); const DIExpression *Expr = computeExprForSpill(Orig, SpillReg); MachineInstrBuilder NewMI = BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc()); |