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| author | Andrew Savonichev <andrew.savonichev@gmail.com> | 2020-12-29 19:49:09 +0300 |
|---|---|---|
| committer | Andrew Savonichev <andrew.savonichev@gmail.com> | 2021-03-04 14:08:19 +0300 |
| commit | d791695cb5172b527e1b0717458d8852abcf34d1 (patch) | |
| tree | d483cd6ed35fd509a1577fd1c0feab2c62d5474a /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 1584e55a2602cd9fe0db059b06a217822ffac7cd (diff) | |
| download | llvm-d791695cb5172b527e1b0717458d8852abcf34d1.zip llvm-d791695cb5172b527e1b0717458d8852abcf34d1.tar.gz llvm-d791695cb5172b527e1b0717458d8852abcf34d1.tar.bz2 | |
[MCA] Add support for in-order CPUs
This patch adds a pipeline to support in-order CPUs such as ARM
Cortex-A55.
In-order pipeline implements a simplified version of Dispatch,
Scheduler and Execute stages as a single stage. Entry and Retire
stages are common for both in-order and out-of-order pipelines.
Differential Revision: https://reviews.llvm.org/D94928
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions