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| author | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:51:21 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:51:21 +0000 |
| commit | b8a74276368a4b464fb22a3b56ac303b3dd98b85 (patch) | |
| tree | 9408b080b114a0692e0f5986079226daa935a99e /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 8a16769b61c77ebc6682435db2ed1823ae1be0f1 (diff) | |
| download | llvm-b8a74276368a4b464fb22a3b56ac303b3dd98b85.zip llvm-b8a74276368a4b464fb22a3b56ac303b3dd98b85.tar.gz llvm-b8a74276368a4b464fb22a3b56ac303b3dd98b85.tar.bz2 | |
fix a bunch of partially ambiguous patterns on ARM. As an
example, this:
(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))
is ambiguous because DPR contains both f64 and v2f32. tblgen
currently accidentally picks f64 because it's first in the
regclass.
llvm-svn: 97955
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions