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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2021-01-25 07:55:13 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2021-01-25 07:58:12 +0000 |
| commit | 8fbc1437c605fe92c0fa286757e3b287d6b02f05 (patch) | |
| tree | d40e752947d35581af877e70bb13858c863dd2c7 /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 6884fbc2c4fb46d0528c02d16d510f4f725fac11 (diff) | |
| download | llvm-8fbc1437c605fe92c0fa286757e3b287d6b02f05.zip llvm-8fbc1437c605fe92c0fa286757e3b287d6b02f05.tar.gz llvm-8fbc1437c605fe92c0fa286757e3b287d6b02f05.tar.bz2 | |
[AArch64] Merge [US]MULL with half adds and subs into [US]ML[AS]L
This patch adds patterns to teach the AArch64 backend to merge [US]MULL
instructions and adds/subs of half the size into [US]ML[AS]L where we don't use
the top half of the result.
Differential Revision: https://reviews.llvm.org/D95218
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions