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authorAmara Emerson <amara@apple.com>2023-02-23 16:35:39 -0800
committerAmara Emerson <amara@apple.com>2023-04-12 16:43:14 -0700
commit719024a0d02f3da1e08d09613c7cad5b8d6f6d26 (patch)
tree3783c2bed8dc799260b5bf5226afde6277907ae6 /llvm/lib/CodeGen/MachineInstr.cpp
parent29c851f4e2ff9dc55146be88ae0df3d378a7be9f (diff)
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[GlobalISel][NFC] Add MachineInstr::getFirst[N]{Regs,LLTs}() helpers to extract regs & types.
These reduce the typing and clutter from: Register Dst = MI.getOperand(0).getReg(); Register Src1 = MI.getOperand(1).getReg(); Register Src2 = MI.getOperand(2).getReg(); Register Src3 = MI.getOperand(3).getReg(); LLT DstTy = MRI.getType(Dst); ... etc etc To just: auto [Dst, Src1, Src2, Src3] = MI.getFirst4Regs(); auto [DstTy, Src1Ty, Src2Ty, Src3Ty] = MI.getFirst4LLTs(); Or even more concise: auto [Dst, DstTy, Src1, Src1Ty, Src2, Src2Ty, Src3, Src3Ty] = MI.getFirst4RegLLTs(); Differential Revision: https://reviews.llvm.org/D144687
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp76
1 files changed, 76 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 8e0777f..5617cb0 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -149,6 +150,12 @@ MachineRegisterInfo *MachineInstr::getRegInfo() {
return nullptr;
}
+const MachineRegisterInfo *MachineInstr::getRegInfo() const {
+ if (const MachineBasicBlock *MBB = getParent())
+ return &MBB->getParent()->getRegInfo();
+ return nullptr;
+}
+
void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
for (MachineOperand &MO : operands())
if (MO.isReg())
@@ -2378,3 +2385,72 @@ unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
DebugInstrNum = MF.getNewDebugInstrNum();
return DebugInstrNum;
}
+
+std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
+ return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
+ getRegInfo()->getType(getOperand(1).getReg()));
+}
+
+std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
+ return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
+ getRegInfo()->getType(getOperand(1).getReg()),
+ getRegInfo()->getType(getOperand(2).getReg()));
+}
+
+std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
+ return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
+ getRegInfo()->getType(getOperand(1).getReg()),
+ getRegInfo()->getType(getOperand(2).getReg()),
+ getRegInfo()->getType(getOperand(3).getReg()));
+}
+
+std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
+ return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
+ getRegInfo()->getType(getOperand(1).getReg()),
+ getRegInfo()->getType(getOperand(2).getReg()),
+ getRegInfo()->getType(getOperand(3).getReg()),
+ getRegInfo()->getType(getOperand(4).getReg()));
+}
+
+std::tuple<Register, LLT, Register, LLT>
+MachineInstr::getFirst2RegLLTs() const {
+ Register Reg0 = getOperand(0).getReg();
+ Register Reg1 = getOperand(1).getReg();
+ return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
+ getRegInfo()->getType(Reg1));
+}
+
+std::tuple<Register, LLT, Register, LLT, Register, LLT>
+MachineInstr::getFirst3RegLLTs() const {
+ Register Reg0 = getOperand(0).getReg();
+ Register Reg1 = getOperand(1).getReg();
+ Register Reg2 = getOperand(2).getReg();
+ return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
+ getRegInfo()->getType(Reg1), Reg2,
+ getRegInfo()->getType(Reg2));
+}
+
+std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
+MachineInstr::getFirst4RegLLTs() const {
+ Register Reg0 = getOperand(0).getReg();
+ Register Reg1 = getOperand(1).getReg();
+ Register Reg2 = getOperand(2).getReg();
+ Register Reg3 = getOperand(3).getReg();
+ return std::tuple(
+ Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
+ Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));
+}
+
+std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register,
+ LLT>
+MachineInstr::getFirst5RegLLTs() const {
+ Register Reg0 = getOperand(0).getReg();
+ Register Reg1 = getOperand(1).getReg();
+ Register Reg2 = getOperand(2).getReg();
+ Register Reg3 = getOperand(3).getReg();
+ Register Reg4 = getOperand(4).getReg();
+ return std::tuple(
+ Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
+ Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),
+ Reg4, getRegInfo()->getType(Reg4));
+}