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author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-04-24 14:32:06 +0800 |
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committer | GitHub <noreply@github.com> | 2024-04-24 14:32:06 +0800 |
commit | 6493da7356541becdf2bf6c141fd619c15dec5d6 (patch) | |
tree | b2f03efaefdec269385cb743c473635568546bba /llvm/lib/CodeGen/MachineInstr.cpp | |
parent | b82a4bfb54284d96ab065596620e260319045330 (diff) | |
download | llvm-6493da7356541becdf2bf6c141fd619c15dec5d6.zip llvm-6493da7356541becdf2bf6c141fd619c15dec5d6.tar.gz llvm-6493da7356541becdf2bf6c141fd619c15dec5d6.tar.bz2 |
[RISCV] Use the store value's VT as the MemoryVT after combining riscv.masked.strided.store (#89874)
According to `RISCVTargetLowering::getTgtMemIntrinsic`, the MemoryVT
is the scalar element VT for strided store and the MemoryVT is the
same as the store value's VT for unit-stride store.
After combining `riscv.masked.strided.store` to `masked.store`, we
just use the scalar element VT to construct `masked.store`, which is
wrong.
With wrong MemoryVT, the DAGCombiner will combine `trunc+masked.store`
to truncated `masked.store` because `TLI.canCombineTruncStore` returns
true.
So, we should use the store value's VT as the MemoryVT.
This fixes #89833.
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions