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authorLuke Lau <luke@igalia.com>2024-03-29 19:45:24 +0800
committerGitHub <noreply@github.com>2024-03-29 19:45:24 +0800
commit2a315d800bb352fe459a012006a42ac7cd63834e (patch)
tree398a7993caa76041bbc4ecb558dff5ad67a1619b /llvm/lib/CodeGen/MachineInstr.cpp
parent1403cf67a628712bddbe0055161ec68c7ebb468d (diff)
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[RISCV] Combine (or disjoint ext, ext) -> vwadd (#86929)
DAGCombiner (or InstCombine) will convert an add to an or if the bits are disjoint, which can prevent what was originally an (add {s,z}ext, {s,z}ext) from being selected as a vwadd. This teaches combineBinOp_VLToVWBinOp_VL to recover it by treating it as an add.
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