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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-14 14:18:56 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-14 14:18:56 +0000 |
| commit | 133716929cdd993a587d8f9d610c87678480bb43 (patch) | |
| tree | 5b103d03a8ea14d96b53f0ffe43664fe9b77f166 /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 9f96f1f17aa9c3db76ca419a60f913015a679bf2 (diff) | |
| download | llvm-133716929cdd993a587d8f9d610c87678480bb43.zip llvm-133716929cdd993a587d8f9d610c87678480bb43.tar.gz llvm-133716929cdd993a587d8f9d610c87678480bb43.tar.bz2 | |
GlobalISel: Use multiple returns for intrinsic structs
This is consistent with what SelectionDAG does and is much easier to
work with than the extract sequence with an artificial wide register.
For the AMDGPU control flow intrinsics, this was producing an s128 for
the i64, i1 tuple return. Any legalization that should apply to a real
s128 value would badly obscure the direct values that need to be seen.
llvm-svn: 356147
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions