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| author | Caroline.Concatto@arm.com <carcon01@ip-10-252-16-47.eu-west-1.compute.internal> | 2022-12-19 14:01:39 +0000 |
|---|---|---|
| committer | Caroline.Concatto@arm.com <carcon01@ip-10-252-16-47.eu-west-1.compute.internal> | 2022-12-19 15:50:24 +0000 |
| commit | 0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0 (patch) | |
| tree | 71c04312ea122004cc63166393c0c79e0f23ab7c /llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | c60e67b1f9df9e7c33addc06d8767b41753b7e6a (diff) | |
| download | llvm-0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0.zip llvm-0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0.tar.gz llvm-0d6d05bb7628c0a13c3a2d83b3f1a3690f63c7f0.tar.bz2 | |
[AArch64] Add alias predicate-as-counter register for PFALSE
According to:
https://developer.arm.com/documentation/ddi0602/2022-09/
PFALSE should:
"...an assembler must also accept predicate-as-counter register
name for the destination predicate register."
Differential Revision: https://reviews.llvm.org/D140301
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
0 files changed, 0 insertions, 0 deletions