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| author | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2024-04-22 17:34:48 +0200 |
|---|---|---|
| committer | Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> | 2024-04-23 13:59:35 +0200 |
| commit | 5fd9bbdea6cc248469d5465de44e747378ffafcb (patch) | |
| tree | b4dc9d7263b777fbaa5566251a73503210afcf50 /llvm/lib/CodeGen/MachineFunctionSplitter.cpp | |
| parent | 0661af893f12c2b09089b4758cf00d9b84230ea0 (diff) | |
| download | llvm-5fd9bbdea6cc248469d5465de44e747378ffafcb.zip llvm-5fd9bbdea6cc248469d5465de44e747378ffafcb.tar.gz llvm-5fd9bbdea6cc248469d5465de44e747378ffafcb.tar.bz2 | |
[DAGCombiner] Pre-commit test case for miscompile bug in combineShiftOfShiftedLogic
DAGCombiner is trying to fold shl over binops, and in the process
combining it with another shl. However it needs to be more careful
to ensure that the sum of the shift counts fits in the type used
for the shift amount.
For example, X86 is using i8 as shift amount type. So we need to
make sure that the sum of the shift amounts isn't greater than 255.
Fix will be applied in a later commit. This only pre-commits the
test case to show that we currently get the wrong result.
Bug was found when testing the C23 BitInt feature.
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunctionSplitter.cpp')
0 files changed, 0 insertions, 0 deletions