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| author | Craig Topper <craig.topper@intel.com> | 2018-09-10 20:31:27 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-09-10 20:31:27 +0000 |
| commit | a5ae613c15a315ea7e575ea94e058cd6524a0aaf (patch) | |
| tree | 6bcf546f72b55d53ccfeb5a87451c269a288c443 /llvm/lib/CodeGen/MachineFunctionPass.cpp | |
| parent | 8eeb16f5d1008a3d3fc89e88d92b3bcebc36bba2 (diff) | |
| download | llvm-a5ae613c15a315ea7e575ea94e058cd6524a0aaf.zip llvm-a5ae613c15a315ea7e575ea94e058cd6524a0aaf.tar.gz llvm-a5ae613c15a315ea7e575ea94e058cd6524a0aaf.tar.bz2 | |
[X86] Mark the ISD::SETLT/SETLE condition codes as illegal for v32i16/v64i8 to match the other vector types.
I'm having a hard time finding a test case for this, but we should be consistent here. The fact that we canonicalize all zeros and all ones constants to vXi32 and all other constants to loads makes this hard to hit the easy DAG combine infinite loop we get for some of the other types.
llvm-svn: 341859
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunctionPass.cpp')
0 files changed, 0 insertions, 0 deletions