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| author | Andrzej Warzynski <andrzej.warzynski@arm.com> | 2020-02-21 13:59:02 +0000 |
|---|---|---|
| committer | Andrzej Warzynski <andrzej.warzynski@arm.com> | 2020-02-27 12:56:33 +0000 |
| commit | fa9439fac84ea4eb4050aa1ae150c0ec2cf86c20 (patch) | |
| tree | 90cb7cc3c5be42858c3ee9632b1774547d607f99 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 5122e828701c88f8d53ee881bc68f3904454d154 (diff) | |
| download | llvm-fa9439fac84ea4eb4050aa1ae150c0ec2cf86c20.zip llvm-fa9439fac84ea4eb4050aa1ae150c0ec2cf86c20.tar.gz llvm-fa9439fac84ea4eb4050aa1ae150c0ec2cf86c20.tar.bz2 | |
[AArch64][SVE] Add intrinsics for first-faulting gather loads
Summary:
The following intrinsics are added:
* @llvm.aarch64.sve.ldff1.gather
* @llvm.aarch64.sve.ldff1.gather.index
* @llvm.aarch64.sve.ldff1.gather_sxtw
* @llvm.aarch64.sve.ldff1.gather.uxtw
* @llvm.aarch64.sve.ldff1.gather_sxtw.index
* @llvm.aarch64.sve.ldff1.gather.uxtw.index
* @llvm.aarch64.sve.ldff1.gather.scalar.offset
Although this patch is quite substantial, the vast majority of the
implementation is just a 'copy & paste' of the implementation of regular
gather loads, including tests. There's only a handful of new
definitions:
* AArch64ISD nodes defined in AArch64ISelLowering.h (e.g. GLDFF1)
* Seleciton DAG Types in AArch64SVEInstrInfo.td (e.g.
AArch64ldff1_gather)
* intrinsics in IntrinsicsAArch64.td (e.g. aarch64_sve_ldff1_gather)
* Pseudo instructions in SVEInstrFormats.td to workaround the issue of
use-before-def for the FFR register.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D75128
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions