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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-02-09 21:15:03 +0000 |
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| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-02-09 21:15:03 +0000 |
| commit | e82e17d4d4cac8b2df00094e80d5e1cb22795664 (patch) | |
| tree | ee95862b82b69a606eaf05e1b5d77e2db59129f5 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | dd262222b403dcfc5aef8fe4c49678ac5675a276 (diff) | |
| download | llvm-e82e17d4d4cac8b2df00094e80d5e1cb22795664.zip llvm-e82e17d4d4cac8b2df00094e80d5e1cb22795664.tar.gz llvm-e82e17d4d4cac8b2df00094e80d5e1cb22795664.tar.bz2 | |
[X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions