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| author | Craig Topper <craig.topper@gmail.com> | 2020-03-07 16:14:26 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2020-03-07 16:14:26 -0800 |
| commit | d81d451442d758dcd4f8d59162cf46c8386bef2d (patch) | |
| tree | 71a424cc002efaa3a82825806a90507fff251102 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | d41ea65ee8e964953a324b394bcb8279af7510fd (diff) | |
| download | llvm-d81d451442d758dcd4f8d59162cf46c8386bef2d.zip llvm-d81d451442d758dcd4f8d59162cf46c8386bef2d.tar.gz llvm-d81d451442d758dcd4f8d59162cf46c8386bef2d.tar.bz2 | |
[X86] Add DAG combine to replace vXi64 vzext_movl+scalar_to_vector with vYi32 vzext_movl+scalar_to_vector if the upper 32 bits of the scalar are zero.
We can just use a 32-bit copy and zero in the SSE domain when we
zero the upper bits.
Remove an isel pattern that becomes dead with this.
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions