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| author | John Brawn <john.brawn@arm.com> | 2025-06-18 16:16:52 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-18 16:16:52 +0100 |
| commit | b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa (patch) | |
| tree | 7b2aac63ba566a5aa7a7c8e52c35d9450375a8c3 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | e4c3b037bc7f5d9a8089de4c509d3e6034735891 (diff) | |
| download | llvm-b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa.zip llvm-b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa.tar.gz llvm-b53c1e4ee810ac21dab5d27413af1f31a6a4cbfa.tar.bz2 | |
[AArch64] Add ISel for postindex ld1/st1 in big-endian (#144387)
When big-endian we need to use ld1/st1 for vector loads and stores so
that we get the elements in the correct order, but this prevents
postindex addressing from being used. Fix this by adding the appropriate
ISel patterns, plus the relevant changes in ISelLowering and
ISelDAGToDAG to cause postindex addressing to be used.
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions