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| author | Craig Topper <craig.topper@intel.com> | 2019-06-13 07:11:02 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-06-13 07:11:02 +0000 |
| commit | b1daec0eae60c6b86d5c7f4712e4edc42c8e4832 (patch) | |
| tree | a750ed67bd8490b58b0123617f90fe8e9e12cf44 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 1f053207638598f51910b839157a08fc48b42323 (diff) | |
| download | llvm-b1daec0eae60c6b86d5c7f4712e4edc42c8e4832.zip llvm-b1daec0eae60c6b86d5c7f4712e4edc42c8e4832.tar.gz llvm-b1daec0eae60c6b86d5c7f4712e4edc42c8e4832.tar.bz2 | |
[X86] Correct instruction operands in evex-to-vex-compress.mir to be closer to real instructions.
$noreg was being used way more than it should have. We also had
xmm registers in addressing modes.
Mostly found by hacking the machine verifier to do some stricter
checking that happened to work for this test, but not sure if
generally applicable for other tests or other targets.
llvm-svn: 363231
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions