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| author | Craig Topper <craig.topper@sifive.com> | 2024-11-07 13:24:22 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-07 13:24:22 -0800 |
| commit | 87feafc391ab1e35997994ad378af727e4947c67 (patch) | |
| tree | b1553f3ea55cc525544fda21434e98a10c232f26 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 1f2509993e6e0717b547b5214b06550af4f3008f (diff) | |
| download | llvm-87feafc391ab1e35997994ad378af727e4947c67.zip llvm-87feafc391ab1e35997994ad378af727e4947c67.tar.gz llvm-87feafc391ab1e35997994ad378af727e4947c67.tar.bz2 | |
[RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to
remove i32 from the GPR register class.
RORW/ROLW target opcodes are added to match SelectionDAG.
The regression in rv64zbb-zbkb.ll requires factoring
isSExtCheaperThanZExt into the G_ANYEXT constant folder. That requires
some interface changes so I didn't do it in this patch.
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions