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| author | Eli Friedman <efriedma@codeaurora.org> | 2018-11-07 21:08:13 +0000 |
|---|---|---|
| committer | Eli Friedman <efriedma@codeaurora.org> | 2018-11-07 21:08:13 +0000 |
| commit | 7d7d41debc9abdda7b3710cdabe2bc64e03d5578 (patch) | |
| tree | f30f2999d2cca4812cae6a154fe5d8cf16d33087 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 3c5d23912b2a6abe4672679ff2c880d562167e37 (diff) | |
| download | llvm-7d7d41debc9abdda7b3710cdabe2bc64e03d5578.zip llvm-7d7d41debc9abdda7b3710cdabe2bc64e03d5578.tar.gz llvm-7d7d41debc9abdda7b3710cdabe2bc64e03d5578.tar.bz2 | |
[ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering.
The lowering was missing live-ins in certain cases, like a sequence of
multiple tMOVCCr_pseudo instructions. This would lead to a verifier
failure, and on pre-v6 Thumb CPSR would be incorrectly clobbered.
For reasons I don't completely understand, it's hard to get a sequence
of multiple tMOVCCr_pseudo instructions; the issue only seems to show up
with 64-bit comparisons where the result is zero-extended. I added some
extra testcases in case that changes in the future. Probably some
optimization opportunities here if anyone is interested. (@test_slt_not
is the case that was getting miscompiled.)
The code to check the liveness of CPSR was stolen from
X86ISelLowering.cpp; maybe it could be refactored into common helper,
but I have no idea where to put it.
Differential Revision: https://reviews.llvm.org/D54192
llvm-svn: 346355
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions