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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-10-15 13:07:32 -0700 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-10-18 01:44:25 -0700 |
| commit | 7cdb1df8c70425b30905418636f9008cf8d3a844 (patch) | |
| tree | caa75c8fff034fcfcf0a8c30db5a70cf56d0681f /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 605efd5dd5bf5f174df7cbd6be9d4e06d6e6249d (diff) | |
| download | llvm-7cdb1df8c70425b30905418636f9008cf8d3a844.zip llvm-7cdb1df8c70425b30905418636f9008cf8d3a844.tar.gz llvm-7cdb1df8c70425b30905418636f9008cf8d3a844.tar.bz2 | |
[AMDGPU] Divergence driven selection for fused bitlogic
The change adds divergence predicates for fused logical operations.
The problem with selecting a scalar fused op such as S_NOR_B32 is
that it does not have a VALU counterpart and will be split in
moveToVALU. At the same time it prevents selection of a better
opcode on the VALU side (such as V_OR3_B32) which does not have a
counterpart on SALU side.
XNOR opcodes are left as is and selected as scalar to get advantage
of the SIInstrInfo::lowerScalarXnor() code which can commute
operations to keep one of two opcodes on SALU if possible. See
xnor.ll test for this.
Differential Revision: https://reviews.llvm.org/D111907
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions