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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-25 10:02:21 +0000 |
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| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-06-25 10:02:21 +0000 |
| commit | 6d9b9e125dd69e639d30cd80ef1a64726da26927 (patch) | |
| tree | 5420996aa0446802f489b674912d9079b7c1ccf7 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | d99cca2c7a30fd9b0a7df3b509eb5c9b39cd0d3a (diff) | |
| download | llvm-6d9b9e125dd69e639d30cd80ef1a64726da26927.zip llvm-6d9b9e125dd69e639d30cd80ef1a64726da26927.tar.gz llvm-6d9b9e125dd69e639d30cd80ef1a64726da26927.tar.bz2 | |
[X86] Add target combine rule to select ADDSUB instructions from a build_vector
This patch teaches the backend how to combine a build_vector that implements
an 'addsub' between packed float vectors into a sequence of vector add
and vector sub followed by a VSELECT.
The new VSELECT is expected to be lowered into a BLENDI.
At ISel stage, the sequence 'vector add + vector sub + BLENDI' is
pattern-matched against ISel patterns added at r211427 to select
'addsub' instructions.
Added three more ISel patterns for ADDSUB.
Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub'
instructions.
llvm-svn: 211679
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions