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| author | Sam Parker <sam.parker@arm.com> | 2020-03-23 08:39:53 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2020-03-23 08:39:53 +0000 |
| commit | 62fdb1f534b73589187f2dca243c1e30865a734f (patch) | |
| tree | ef7996d9985d7c6b16af84d39771ae53cd59ca22 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 8e45eaf1da56d895a74fb2689590c8b76479b484 (diff) | |
| download | llvm-62fdb1f534b73589187f2dca243c1e30865a734f.zip llvm-62fdb1f534b73589187f2dca243c1e30865a734f.tar.gz llvm-62fdb1f534b73589187f2dca243c1e30865a734f.tar.bz2 | |
[DAGCombine] Skip PostInc combine with later users
When decided whether to generate a post-inc load/store, look at the
other memory nodes that use the same base address and, if any proceed
the current node, then don't do the combine.
The change only seems to be affecting the Arm backend, which I was
surprised at, but it appears to fix a lot of our issues around MVE
masked load/stores having to store a temporary address after an early
post-increment on a shared base address.
Differential Revision: https://reviews.llvm.org/D75847
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions