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| author | Lei Liu <lei.liu2@windriver.com> | 2016-09-29 01:05:48 +0000 |
|---|---|---|
| committer | Lei Liu <lei.liu2@windriver.com> | 2016-09-29 01:05:48 +0000 |
| commit | 361615cfd0ceccd6bc909e16cd81802e04e9c4eb (patch) | |
| tree | 281aa5bee56a1fb92c52127e10502942d1565fd6 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 790ad869ac05d6d94dc7889f3e65e8bc7320366b (diff) | |
| download | llvm-361615cfd0ceccd6bc909e16cd81802e04e9c4eb.zip llvm-361615cfd0ceccd6bc909e16cd81802e04e9c4eb.tar.gz llvm-361615cfd0ceccd6bc909e16cd81802e04e9c4eb.tar.bz2 | |
AArch64: Set shift bit of TLSLE HI12 add instruction
Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.
Reviewers: t.p.northover, peter.smith, rovka
Subscribers: salim.nasser, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D24702
llvm-svn: 282661
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions