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| author | Craig Topper <craig.topper@sifive.com> | 2021-07-06 09:55:57 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-07-06 10:24:31 -0700 |
| commit | 2b5e53111a24eebaa025d12832380638cb0598a1 (patch) | |
| tree | b42f9c638edf83a0fd2dc8b3b9d0601736a47833 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 846a530e7db28bdd50c9a9fb08cddc210134b579 (diff) | |
| download | llvm-2b5e53111a24eebaa025d12832380638cb0598a1.zip llvm-2b5e53111a24eebaa025d12832380638cb0598a1.tar.gz llvm-2b5e53111a24eebaa025d12832380638cb0598a1.tar.bz2 | |
[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.
This adds a DAG combine to detect sext/zext inputs and emit a
new ISD opcode. The extends will either be removed or replaced
with narrower extends.
Isel patterns are used to match add and widening mul to vwmacc
similar to the recently added vmacc patterns.
There's still some work to be to match vmulsu.
We should also rewrite splats that were extended as scalars and
then splatted.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D104802
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions