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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-06-26 19:02:46 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-08-20 16:15:53 -0400 |
| commit | 18b218007db69627bb651bb2a548afe92d615cd3 (patch) | |
| tree | f42373472d45260f9e50ce8a7142037a54831d07 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 54d8ded4b19aeba05006367766d148d34be01c02 (diff) | |
| download | llvm-18b218007db69627bb651bb2a548afe92d615cd3.zip llvm-18b218007db69627bb651bb2a548afe92d615cd3.tar.gz llvm-18b218007db69627bb651bb2a548afe92d615cd3.tar.bz2 | |
AMDGPU/GlobalISel: Legalize odd sized loads with widening
Custom lower and widen odd sized loads up to the alignment. The
default set of legalization actions doesn't have a way to represent
this. This fixes naturally aligned <3 x s8> and <3 x s16> loads.
This also starts moving towards eliminating the buggy and
overcomplicated legalization rules for narrowing. All the memory size
changes should be done in the lower or custom action, not NarrowScalar
/ FewerElements. These currently have redundant and ambiguous code
with the lower action.
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions