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| author | Francesco Petrogalli <francesco.petrogalli@arm.com> | 2020-02-26 22:19:42 +0000 |
|---|---|---|
| committer | Francesco Petrogalli <francesco.petrogalli@arm.com> | 2020-03-16 18:52:35 +0000 |
| commit | 0f2b68d9c70eb16e94a50a06c9c111cc2858fec8 (patch) | |
| tree | fef99c6989c9f929250f41312e5bd9aab6e2bac2 /llvm/lib/CodeGen/MachineFunction.cpp | |
| parent | 0616e9964b9ef2e2cb12790515610e7cdd0042e3 (diff) | |
| download | llvm-0f2b68d9c70eb16e94a50a06c9c111cc2858fec8.zip llvm-0f2b68d9c70eb16e94a50a06c9c111cc2858fec8.tar.gz llvm-0f2b68d9c70eb16e94a50a06c9c111cc2858fec8.tar.bz2 | |
Implement IR intrinsics for gather prefetch.
Summary:
Intrinsics and relative codegen has been implemented for the following
SVE instructions:
1. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit scaled offset
2. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] -> 32-bit unpacked scaled offset
3. PRF<T> <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit scaled offset
4. PRF<T> <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
5. PRF<T> <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
The instructions are associated the following intrinsics, respectively:
1. void @llvm.aarch64.sve.gather.prf<T>.scaled.<mod>.nx4vi32(
i8* %base,
<vscale x 4 x i32> %offset,
<vscale x 4 x i1> %Pg,
i32 %prfop)
2. void @llvm.aarch64.sve.gather.prf<T>.scaled.<mod>.nx2vi32(
i8* %base,
<vscale x 2 x i32> %offset,
<vscale x 2 x i1> %Pg,
i32 %prfop)
3. void @llvm.aarch64.sve.gather.prf<T>.scaled.nx2vi64(
i8* %base,
<vscale x 2 x i64> %offset,
<vscale x 2 x i1> %Pg,
i32 %prfop)
4. void @llvm.aarch64.sve.gather.prf<T>.nx4vi32(
<vscale x 4 x i32> %bases,
i64 %imm,
<vscale x 4 x i1> %Pg,
i32 %prfop)
5. void @llvm.aarch64.sve.gather.prf<T>.nx2vi64(
<vscale x 2 x i64> %bases,
i64 %imm,
<vscale x 2 x i1> %Pg,
i32 %prfop)
The intrinsics are the IR counterpart of the following SVE ACLE functions:
* void svprf<T>(svbool_t pg, const void *base, svprfop op)
* void svprf<T>_vnum(svbool_t pg, const void *base, int64_t vnum, svprfop op)
* void svprf<T>_gather[_u32base](svbool_t pg, svuint32_t bases, svprfop op)
* void svprf<T>_gather[_u64base](svbool_t pg, svuint64_t bases, svprfop op)
* void svprf<T>_gather_[s32]offset(svbool_t pg, const void *base, svint32_t offsets, svprfop op)
* void svprf<T>_gather_[u32]offset(svbool_t pg, const void *base, svint32_t offsets, svprfop op)
* void svprf<T>_gather_[s64]offset(svbool_t pg, const void *base, svint64_t offsets, svprfop op)
* void svprf<T>_gather_[u64]offset(svbool_t pg, const void *base, svint64_t offsets, svprfop op)
* void svprf<T>_gather[_u32base]_offset(svbool_t pg, svuint32_t bases, int64_t offset, svprfop op)
* void svprf<T>_gather[_u64base]_offset(svbool_t pg, svuint64_t bases,int64_t offset, svprfop op)
Reviewers: andwar, sdesmalen, efriedma, rengolin
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D75580
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions