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| author | Qiu Chaofan <qiucofan@cn.ibm.com> | 2020-08-10 18:25:01 +0800 |
|---|---|---|
| committer | Qiu Chaofan <qiucofan@cn.ibm.com> | 2020-08-10 18:27:45 +0800 |
| commit | dbcfbffc7ae46cc7b84257787681676144a1bd5f (patch) | |
| tree | 06fcfd5bde200bad0f714e2aa54a2f062514994a /llvm/lib/CodeGen/MachineDebugify.cpp | |
| parent | 0b26c9eddc4f0112f18f75f64c0fb4e5839a6795 (diff) | |
| download | llvm-dbcfbffc7ae46cc7b84257787681676144a1bd5f.zip llvm-dbcfbffc7ae46cc7b84257787681676144a1bd5f.tar.gz llvm-dbcfbffc7ae46cc7b84257787681676144a1bd5f.tar.bz2 | |
[PowerPC] Add intrinsic to read or set FPSCR register
This patch introduces two intrinsics: llvm.ppc.setflm and
llvm.ppc.readflm. They read from or write to FPSCR register
(floating-point status & control) which contains rounding mode and
exception status.
To ensure correctness of program, we need to prevent FP operations from
being moved across these intrinsics (mffs/mtfsf instruction), so here I
set them as scheduling boundaries. We can relax such restriction if
FPSCR is modeled well in the future.
Reviewed By: steven.zhang
Differential Revision: https://reviews.llvm.org/D84914
Diffstat (limited to 'llvm/lib/CodeGen/MachineDebugify.cpp')
0 files changed, 0 insertions, 0 deletions