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author | Alexandru Octavian Butiu <alexandru.octavian.butiu@gmail.com> | 2021-07-02 18:50:07 +0800 |
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committer | Kai Luo <lkail@cn.ibm.com> | 2021-07-02 19:27:06 +0800 |
commit | e90c6f559637446330335ce6638ae3e3827992e8 (patch) | |
tree | e46fb7e756fb43cbf0ffcf0da93e756ecc2d7034 /llvm/lib/CodeGen/MachineCopyPropagation.cpp | |
parent | c142c06c19b3725f26f33652db098a2302586f22 (diff) | |
download | llvm-e90c6f559637446330335ce6638ae3e3827992e8.zip llvm-e90c6f559637446330335ce6638ae3e3827992e8.tar.gz llvm-e90c6f559637446330335ce6638ae3e3827992e8.tar.bz2 |
[MachineCopyPropagation] Fix differences in code gen when compiling with -g
Fixes bugs [[ https://bugs.llvm.org/show_bug.cgi?id=50580 | 50580 ]] and [[ https://bugs.llvm.org/show_bug.cgi?id=49446 | 49446 ]]
When compiling with -g "DBG_VALUE <reg>" instructions are added in the MIR, if such a instruction is inserted between instructions that use <reg> then MachineCopyPropagation invalidates <reg> , this causes some copies to not be propagated and causes differences in code generation (ex bugs 50580 and 49446 ). DBG_VALUE instructions should be ignored since they don't actually modify the register.
Reviewed By: lkail
Differential Revision: https://reviews.llvm.org/D104394
Diffstat (limited to 'llvm/lib/CodeGen/MachineCopyPropagation.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineCopyPropagation.cpp | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 7bac590..10b74f5 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -870,12 +870,32 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock( if (MO.isDef()) Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI); - if (MO.readsReg()) - Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI); + if (MO.readsReg()) { + if (MO.isDebug()) { + // Check if the register in the debug instruction is utilized + // in a copy instruction, so we can update the debug info if the + // register is changed. + for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid(); + ++RUI) { + if (auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *TRI)) { + CopyDbgUsers[Copy].insert(MI); + } + } + } else { + Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI); + } + } } } for (auto *Copy : MaybeDeadCopies) { + + Register Src = Copy->getOperand(1).getReg(); + Register Def = Copy->getOperand(0).getReg(); + SmallVector<MachineInstr *> MaybeDeadDbgUsers(CopyDbgUsers[Copy].begin(), + CopyDbgUsers[Copy].end()); + + MRI->updateDbgUsersToReg(Src.asMCReg(), Def.asMCReg(), MaybeDeadDbgUsers); Copy->eraseFromParent(); ++NumDeletes; } |