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| author | Craig Topper <craig.topper@sifive.com> | 2023-09-22 15:54:48 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-09-22 17:04:11 -0700 |
| commit | 7cd01afb73a2b88ab410404932ebdaf04becd883 (patch) | |
| tree | aee416d4c1479d8b5aedd89753fb3f0a076c6ff9 /llvm/lib/CodeGen/MachineCopyPropagation.cpp | |
| parent | 12ee3a6f53db552b121b733ca21fb8c4f048398a (diff) | |
| download | llvm-7cd01afb73a2b88ab410404932ebdaf04becd883.zip llvm-7cd01afb73a2b88ab410404932ebdaf04becd883.tar.gz llvm-7cd01afb73a2b88ab410404932ebdaf04becd883.tar.bz2 | |
[RISCV][GISel] Add test showing missed opportunity to use X0 for the LHS of sub for negate.
I had to disable the late copy propagation pass that can see through
the ADDI we were previously emitting. We really want to get this
in the register coalescer if not even earlier.
Diffstat (limited to 'llvm/lib/CodeGen/MachineCopyPropagation.cpp')
0 files changed, 0 insertions, 0 deletions