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| author | Allen <zhongyunde@huawei.com> | 2024-04-24 19:44:15 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-24 19:44:15 +0800 |
| commit | af81d8ec224900de7a4d2c96a675269499b55a0c (patch) | |
| tree | 0b2f97a293cc470d0f9cc910dc50fc95b58f9a89 /llvm/lib/CodeGen/MachineCombiner.cpp | |
| parent | c81ec1f35c8226a13df4e2988d3be7b45ebd4e85 (diff) | |
| download | llvm-af81d8ec224900de7a4d2c96a675269499b55a0c.zip llvm-af81d8ec224900de7a4d2c96a675269499b55a0c.tar.gz llvm-af81d8ec224900de7a4d2c96a675269499b55a0c.tar.bz2 | |
[AArch64][CodeGen] Add patterns for small negative VScale const (#89607)
On AArch64, rdvl can accept a nagative value, while cntd/cntw/cnth can't.
As we do support VScale with a negative multiply value, so we did not limit
the negative value and instead took the hit of having the extra patterns according PR88108.
Also add NoUseScalarIncVL to avoid affecting patterns works for -mattr=+use-scalar-inc-vl
Fix https://github.com/llvm/llvm-project/issues/84620
Diffstat (limited to 'llvm/lib/CodeGen/MachineCombiner.cpp')
0 files changed, 0 insertions, 0 deletions