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| author | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-28 17:49:29 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-28 17:49:29 +0000 |
| commit | fded35952a9386933b02701baaba8a0eaee2f259 (patch) | |
| tree | 7249a95b642ec84ef4f69e48ca79b682d3b31675 /llvm/lib/CodeGen/MachineCodeEmitter.cpp | |
| parent | 2c35144ce5dad71f8c2ab7eb96a392c3b3db3117 (diff) | |
| download | llvm-fded35952a9386933b02701baaba8a0eaee2f259.zip llvm-fded35952a9386933b02701baaba8a0eaee2f259.tar.gz llvm-fded35952a9386933b02701baaba8a0eaee2f259.tar.bz2 | |
Fixed ordering of elements in instructions: although the binary instructions
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.
Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.
llvm-svn: 6384
Diffstat (limited to 'llvm/lib/CodeGen/MachineCodeEmitter.cpp')
0 files changed, 0 insertions, 0 deletions