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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 23:53:23 +0000 |
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| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-04 23:53:23 +0000 |
| commit | c300ef0e5017dd9ed66646214fbaf8d8b5e835b0 (patch) | |
| tree | 3c8810c28a6b828385ed6421142ffa559646581c /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | adb50a7a09a86e9198a3a646e382396a261a2d8f (diff) | |
| download | llvm-c300ef0e5017dd9ed66646214fbaf8d8b5e835b0.zip llvm-c300ef0e5017dd9ed66646214fbaf8d8b5e835b0.tar.gz llvm-c300ef0e5017dd9ed66646214fbaf8d8b5e835b0.tar.bz2 | |
Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.
The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.
Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.
llvm-svn: 159727
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions