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| author | Brandon Wu <brandon.wu@sifive.com> | 2024-01-24 11:30:12 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-24 11:30:12 +0800 |
| commit | 33d804c6c2786cbbbc13743060f08d679941e0a4 (patch) | |
| tree | aa4bd7d7e7122033aec2f84c6483c9b7ea1184da /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | 7251243315ef66f9b3f32e6f8e9536f701aa0d0a (diff) | |
| download | llvm-33d804c6c2786cbbbc13743060f08d679941e0a4.zip llvm-33d804c6c2786cbbbc13743060f08d679941e0a4.tar.gz llvm-33d804c6c2786cbbbc13743060f08d679941e0a4.tar.bz2 | |
[RISCV] Allow VCIX with SE to reorder (#77049)
This patch allows VCIX instructions that have side effect to be
reordered
with memory and other side effecting instructions. However we don't want
VCIX instructions to be reordered with each other, so we propose a dummy
register called VCIX_STATE and make these instructions implicitly define
and use
it.
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions