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authorNico Weber <thakis@chromium.org>2025-05-04 17:36:08 -0400
committerNico Weber <thakis@chromium.org>2025-05-04 17:36:52 -0400
commit1d955489c3c2fc2da89826a5cd6bf7954cf133b7 (patch)
tree5fc03555617836d06996da5ef9f45dbfbe3b4c0e /llvm/lib/CodeGen/MachineCSE.cpp
parentd3e792cec1c29d2abd52983cc200cd1551ceb2cd (diff)
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Revert "[CodeGen] Use range-based for loops (NFC) (#138434)"
This reverts commit a9699a334bc9666570418a3bed9520bcdc21518b. Breaks CodeGen/AMDGPU/collapse-endcf.ll in several configs (sanitizer builds; macOS; possibly more), see comments on https://github.com/llvm/llvm-project/pull/138434
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineCSE.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index bebdead..6d14509 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -325,8 +325,9 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
}
// Finally, add all defs to PhysRefs as well.
- for (const auto &Def : PhysDefs)
- for (MCRegAliasIterator AI(Def.second, TRI, true); AI.isValid(); ++AI)
+ for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
+ for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
+ ++AI)
PhysRefs.insert(*AI);
return !PhysRefs.empty();
@@ -347,8 +348,9 @@ bool MachineCSEImpl::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
return false;
- for (const auto &PhysDef : PhysDefs) {
- if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second))
+ for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
+ if (MRI->isAllocatable(PhysDefs[i].second) ||
+ MRI->isReserved(PhysDefs[i].second))
// Avoid extending live range of physical registers if they are
//allocatable or reserved.
return false;