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| author | Baptiste Saleil <baptiste.saleil@ibm.com> | 2020-09-21 10:23:51 -0500 |
|---|---|---|
| committer | Baptiste Saleil <baptiste.saleil@ibm.com> | 2020-09-21 10:27:47 -0500 |
| commit | 1372e23c7d4b25fd23689842246e66f70c949b46 (patch) | |
| tree | e87d9c5d0b8a505a002e64e220fa2d33392a64b1 /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | 5249e6f24876ea577de51ad2f9166a2e466171b9 (diff) | |
| download | llvm-1372e23c7d4b25fd23689842246e66f70c949b46.zip llvm-1372e23c7d4b25fd23689842246e66f70c949b46.tar.gz llvm-1372e23c7d4b25fd23689842246e66f70c949b46.tar.bz2 | |
[PowerPC] Add vector pair load/store instructions and vector pair register class
This patch adds support for the lxvp, lxvpx, plxvp, stxvp, stxvpx and pstxvp
instructions in the PowerPC backend. These instructions allow loading and
storing VSX register pairs. This patch also adds the VSRp register class
definition needed for these instructions.
Differential Revision: https://reviews.llvm.org/D84359
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
0 files changed, 0 insertions, 0 deletions