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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-01-24 09:35:30 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-24 09:35:30 +0700 |
| commit | 0ef39a882bb342982929d2c856d7865de147a3c7 (patch) | |
| tree | e363301d3b1c804c26f36cb6cae81b818ef65025 /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | e06b7030303b50556f0a96948d03adb84a90e536 (diff) | |
| download | llvm-0ef39a882bb342982929d2c856d7865de147a3c7.zip llvm-0ef39a882bb342982929d2c856d7865de147a3c7.tar.gz llvm-0ef39a882bb342982929d2c856d7865de147a3c7.tar.bz2 | |
MachineCSE: Remove check for subreg on a def operand (#124095)
There are no subregister defs in SSA.
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineCSE.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index 728fd2f..bea0eaf 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -187,8 +187,6 @@ bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI, Register SrcReg = DefMI->getOperand(1).getReg(); if (!SrcReg.isVirtual()) continue; - if (DefMI->getOperand(0).getSubReg()) - continue; // FIXME: We should trivially coalesce subregister copies to expose CSE // opportunities on instructions with truncated operands (see // cse-add-with-overflow.ll). This can be done here as follows: |