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| author | Xiang1 Zhang <xiang1.zhang@intel.com> | 2023-04-11 14:57:01 +0800 |
|---|---|---|
| committer | Xiang1 Zhang <xiang1.zhang@intel.com> | 2023-04-20 10:37:46 +0800 |
| commit | f50059b04f2c66192ec99251476eccd062822660 (patch) | |
| tree | 978bdd96d93e18fa6c4265cd1ee34ff8c5788562 /llvm/lib/CodeGen/MachineBlockPlacement.cpp | |
| parent | 3f81d25cee7065a4a7888bbe9ad7138081dcd4cf (diff) | |
| download | llvm-f50059b04f2c66192ec99251476eccd062822660.zip llvm-f50059b04f2c66192ec99251476eccd062822660.tar.gz llvm-f50059b04f2c66192ec99251476eccd062822660.tar.bz2 | |
[X86] combineConcatVectorOps - remove FADD/FSUB/FMUL handling
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D147996
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockPlacement.cpp')
0 files changed, 0 insertions, 0 deletions