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| author | David Sherwood <david.sherwood@arm.com> | 2022-11-01 17:11:47 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2022-11-07 15:51:09 +0000 |
| commit | a9d7b18b4a853daa8fecb5d5863af211841de762 (patch) | |
| tree | 4e29670982fc4ceb679784ab72fb0685c50c2c76 /llvm/lib/CodeGen/MachineBlockPlacement.cpp | |
| parent | a8c24d57b81703b5730460d7cb12af9783a02539 (diff) | |
| download | llvm-a9d7b18b4a853daa8fecb5d5863af211841de762.zip llvm-a9d7b18b4a853daa8fecb5d5863af211841de762.tar.gz llvm-a9d7b18b4a853daa8fecb5d5863af211841de762.tar.bz2 | |
[AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d
This patch adds the assembly/disassembly for the following instructions:
st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137245
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockPlacement.cpp')
0 files changed, 0 insertions, 0 deletions