aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/MachineBlockPlacement.cpp
diff options
context:
space:
mode:
authorBenjamin Maxwell <benjamin.maxwell@arm.com>2024-07-24 10:06:34 +0100
committerGitHub <noreply@github.com>2024-07-24 10:06:34 +0100
commit7fad04e94b7b594389111ae7eca0883ef18dc90b (patch)
tree2510d3cfc7cd8eed5c2a9081411b2f8cf7308d2e /llvm/lib/CodeGen/MachineBlockPlacement.cpp
parent6a1b119035bd329c54f6b5438e6989e49dcb0adb (diff)
downloadllvm-7fad04e94b7b594389111ae7eca0883ef18dc90b.zip
llvm-7fad04e94b7b594389111ae7eca0883ef18dc90b.tar.gz
llvm-7fad04e94b7b594389111ae7eca0883ef18dc90b.tar.bz2
[LSR] Fix matching vscale immediates (#100080)
Somewhat confusingly a `SCEVMulExpr` is a `SCEVNAryExpr`, so can have > 2 operands. Previously, the vscale immediate matching did not check the number of operands of the `SCEVMulExpr`, so would ignore any operands after the first two. This led to incorrect codegen (and results) for ArmSME in IREE (https://github.com/iree-org/iree), which sometimes addresses things that are a `vscale * vscale` multiple away. The test added with this change shows an example reduced from IREE. The second write should be offset from the first `16 * vscale * vscale` (* 4 bytes), however, previously LSR dropped the second vscale and instead offset the write by `#4, mul vl`, which is an offset of `16 * vscale` (* 4 bytes).
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockPlacement.cpp')
0 files changed, 0 insertions, 0 deletions