diff options
| author | Nirvedh Meshram <96096277+nirvedhmeshram@users.noreply.github.com> | 2024-09-24 12:24:59 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-24 12:24:59 -0500 |
| commit | 234193bae6cf8b19703c6e543b100517bb99a9f7 (patch) | |
| tree | 3e490fe9b1d80a2c196dc1f5e73c58fdd4af8899 /llvm/lib/CodeGen/MachineBlockPlacement.cpp | |
| parent | f4042077e2e3946ee35c1df8cab8237de6086480 (diff) | |
| download | llvm-234193bae6cf8b19703c6e543b100517bb99a9f7.zip llvm-234193bae6cf8b19703c6e543b100517bb99a9f7.tar.gz llvm-234193bae6cf8b19703c6e543b100517bb99a9f7.tar.bz2 | |
[mlir][linalg] Vectorization support for convolution of i1 type (#109480)
Normally convolutions present with the following linalg op region
```
^bb0(%arg14: i4, %arg15: i4, %arg16: i4):
%17 = arith.muli %arg14, %arg15 : i4
%18 = arith.addi %arg16, %17 : i4
linalg.yield %18 : i4
```
However, for i1 due to strength reduction we get something like
```
^bb0(%arg14: i1, %arg15: i1, %arg16: i1):
%17 = arith.andi %arg14, %arg15 : i1
%18 = arith.ori %arg16, %17 : i1
linalg.yield %18 : i1
```
This PR updates the logic to support this region for i1 types.
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockPlacement.cpp')
0 files changed, 0 insertions, 0 deletions