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| author | Thomas Lively <tlively@google.com> | 2020-12-22 20:06:12 -0800 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2020-12-22 20:06:12 -0800 |
| commit | efe7f5ede0b3276f3f43daca46410bb7978221fb (patch) | |
| tree | ba535f5f6707b444bb6967b2fbcae1ed55bf3d30 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | e6fde1ae7df0b019392352b61d898c9b83b775fa (diff) | |
| download | llvm-efe7f5ede0b3276f3f43daca46410bb7978221fb.zip llvm-efe7f5ede0b3276f3f43daca46410bb7978221fb.tar.gz llvm-efe7f5ede0b3276f3f43daca46410bb7978221fb.tar.bz2 | |
[WebAssembly][NFC] Refactor SIMD load/store tablegen defs
Introduce `Vec` records, each bundling all information related to a single SIMD
lane interpretation. This lets TableGen definitions take a single Vec parameter
from which they can extract information rather than taking multiple redundant
parameters. This commit refactors all of the SIMD load and store instruction
definitions to use the new `Vec`s. Subsequent commits will similarly refactor
additional instruction definitions.
Differential Revision: https://reviews.llvm.org/D93660
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions