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| author | Michael Maitland <michaeltmaitland@gmail.com> | 2023-11-07 06:25:13 -0800 |
|---|---|---|
| committer | Michael Maitland <michaeltmaitland@gmail.com> | 2023-11-15 15:08:29 -0800 |
| commit | dbd884cd3da720b0adbd52142f1426745ab9d181 (patch) | |
| tree | cc53124b38589db581b4d0976870a30ea69b00fa /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | f219e03f3c9bea4220925838c3d57d5a993d4d7a (diff) | |
| download | llvm-dbd884cd3da720b0adbd52142f1426745ab9d181.zip llvm-dbd884cd3da720b0adbd52142f1426745ab9d181.tar.gz llvm-dbd884cd3da720b0adbd52142f1426745ab9d181.tar.bz2 | |
[RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass
Vector Register banks are created for the various register vector
register groupings. getRegBankFromRegClass is implemented to go from
vector TargetRegisterClass to the corresponding vector RegisterBank.
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions