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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-01-20 00:29:59 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-01-20 00:29:59 +0000 |
| commit | bf480554dfb7a8e19bb0527cb12cd3f9c2392ac8 (patch) | |
| tree | 3dcaa04a0871b871b478ca49dceb8b3840d8f5fa /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 245318cb0501a417c5cda39dd00e31f133f12d87 (diff) | |
| download | llvm-bf480554dfb7a8e19bb0527cb12cd3f9c2392ac8.zip llvm-bf480554dfb7a8e19bb0527cb12cd3f9c2392ac8.tar.gz llvm-bf480554dfb7a8e19bb0527cb12cd3f9c2392ac8.tar.bz2 | |
[MIRParser] Allow generic register specification on operand.
This completes r292321 by adding support for generic registers, e.g.:
%2:_(s32) = G_ADD %0, %1
llvm-svn: 292550
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions