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author | Diana <Diana-Magda.Picus@amd.com> | 2023-10-06 09:43:04 +0200 |
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committer | GitHub <noreply@github.com> | 2023-10-06 09:43:04 +0200 |
commit | be382de0596d5d2c7a7ee7363bbb499df731acc6 (patch) | |
tree | 417d7d295633cab059dbad3dffabd860918e4a10 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
parent | 4ccd57ddb11e833f6b2ec2188e73c4ef3a5ab80e (diff) | |
download | llvm-be382de0596d5d2c7a7ee7363bbb499df731acc6.zip llvm-be382de0596d5d2c7a7ee7363bbb499df731acc6.tar.gz llvm-be382de0596d5d2c7a7ee7363bbb499df731acc6.tar.bz2 |
[AMDGPU] Use correct operand order for shifts (#68299)
In a special case in frame index elimination (when the offset is 0), we
generate either a S_LSHR_B32 or a V_LSHRREV_B32 using the same code.
However, they don't expect their operands in the same order - S_LSHR_B32
takes the value to be shifted first and then the shift amount, whereas
V_LSHRREV_B32 has the operands reversed (hence the REV in its name).
Update the code & tests to take this into account. Also remove an
outdated comment (this code is definitely reachable now that non-entry
functions no longer have a fixed emergency scavenge slot).
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions