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| author | Craig Topper <craig.topper@sifive.com> | 2021-06-18 12:10:17 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-06-18 12:16:07 -0700 |
| commit | ac87133f1de902bcc7ab4330e7ac79b2ba376d34 (patch) | |
| tree | a79847bbc59de193997f7f5fe18c13ae1126be61 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 8c2c97287eacda1ed9cbee893054d868e3b990c5 (diff) | |
| download | llvm-ac87133f1de902bcc7ab4330e7ac79b2ba376d34.zip llvm-ac87133f1de902bcc7ab4330e7ac79b2ba376d34.tar.gz llvm-ac87133f1de902bcc7ab4330e7ac79b2ba376d34.tar.bz2 | |
[RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch.
Previously we went directly to unknown state on VTYPE mismatch.
If we instead remember the partial match, we can use this to
still use X0, X0 vsetvli in successors if AVL and needed SEW/LMUL
ratio match.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D104069
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions