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authorMatthew Simpson <mssimpso@codeaurora.org>2017-12-27 15:25:01 +0000
committerMatthew Simpson <mssimpso@codeaurora.org>2017-12-27 15:25:01 +0000
commit9439f54902860be9c097db22a22d3456b83afc14 (patch)
treeb5a8d563f60a3903eea1f9af286e32738ecd415f /llvm/lib/CodeGen/MachineBasicBlock.cpp
parent293f34301eb3409534fd83b71e40f7e0cc8d252c (diff)
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[AArch64] Change order of candidate FMLS patterns
r319980 added new patterns to the machine combiner for transforming (fsub (fmul x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source operand is an fmul are transformed. We previously only matched the case where the second source operand of an fsub was an fmul, transforming (fsub z (fmul x y)) into (fmls z x y). Now, if we have an fsub where both source operands are fmuls, both of the above patterns are applicable. However, the order in which we add the patterns to the list of candidates determines the transformation that takes place, since only the first pattern that matches will be used. This patch changes the order these two patterns are added to the list of candidates such that we prefer the case where the second source operand is an fmul (the fmls case), rather than the other one (the fmla/fneg case). When both source operands are fmuls, this ordering results in fewer instructions. Differential Revision: https://reviews.llvm.org/D41587 llvm-svn: 321491
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
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