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| author | Craig Topper <craig.topper@sifive.com> | 2022-08-16 15:50:24 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-08-16 15:51:07 -0700 |
| commit | 53ce22e42971e2ad1acc561496bdf043d3ab0cfa (patch) | |
| tree | b93328fb43a7572a0d6f02f0b4e80777e6cfaeeb /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 2dfa4b6475f85c9f795647513dbd5f206144c23a (diff) | |
| download | llvm-53ce22e42971e2ad1acc561496bdf043d3ab0cfa.zip llvm-53ce22e42971e2ad1acc561496bdf043d3ab0cfa.tar.gz llvm-53ce22e42971e2ad1acc561496bdf043d3ab0cfa.tar.bz2 | |
Recommit "[RISCV] Use setcc's original SDLoc when inverting it in performSUBCombine."
This time using N1 instead of N0 since N1 points to the original
setcc. This now affects scheduling as I expected.
Original commit message:
We change seteq<->setne but it doesn't change the semantics
of the setcc. We should keep original debug location. This is
consistent with visitXor in the generic DAGCombiner.
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions