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author | Geoff Berry <gberry@codeaurora.org> | 2015-11-11 19:42:52 +0000 |
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committer | Geoff Berry <gberry@codeaurora.org> | 2015-11-11 19:42:52 +0000 |
commit | 2ddfc5e60ffe30504de309ade1005f152e6d04e1 (patch) | |
tree | 440d6cf45973207e3227fb6dc43eb17b27d13345 /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
parent | caab921f8a28834788d76ffa20c2bb9df4ade08b (diff) | |
download | llvm-2ddfc5e60ffe30504de309ade1005f152e6d04e1.zip llvm-2ddfc5e60ffe30504de309ade1005f152e6d04e1.tar.gz llvm-2ddfc5e60ffe30504de309ade1005f152e6d04e1.tar.bz2 |
[DAGCombiner] Improve zextload optimization.
Summary:
Don't fold
(zext (and (load x), cst)) -> (and (zextload x), (zext cst))
if
(and (load x) cst)
will match as a zextload already and has additional users.
For example, the following IR:
%load = load i32, i32* %ptr, align 8
%load16 = and i32 %load, 65535
%load64 = zext i32 %load16 to i64
store i32 %load16, i32* %dst1, align 4
store i64 %load64, i64* %dst2, align 8
used to produce the following aarch64 code:
ldr w8, [x0]
and w9, w8, #0xffff
and x8, x8, #0xffff
str w9, [x1]
str x8, [x2]
but with this change produces the following aarch64 code:
ldrh w8, [x0]
str w8, [x1]
str x8, [x2]
Reviewers: resistor, mcrosier
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D14340
llvm-svn: 252789
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions