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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-10-21 14:27:03 -0700 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-10-26 14:40:42 -0700 |
| commit | 038d884a50a4e72d3f65a315d28d35bda024cb4a (patch) | |
| tree | 546c4153edcef82bcc1f135beb2b2821b59a3bec /llvm/lib/CodeGen/MachineBasicBlock.cpp | |
| parent | c551ba0e90bd2b49ef501d591f8362ba44e5484d (diff) | |
| download | llvm-038d884a50a4e72d3f65a315d28d35bda024cb4a.zip llvm-038d884a50a4e72d3f65a315d28d35bda024cb4a.tar.gz llvm-038d884a50a4e72d3f65a315d28d35bda024cb4a.tar.bz2 | |
[AMDGPU] Use flat scratch instructions where available
The support is disabled by default. So far there is instruction
selection, spilling, and frame elimination. It also changes SP
from unswizzled to swizzled as used by flat scratch instructions,
so it cannot be mixed with MUBUF stack access.
At the very least missing:
- GlobalISel;
- Some optimizations in frame elimination in between vector
and scalar ALU;
- It shall finally allow to always materialize frame index
as an SGPR, but that is not implemented and frame elimination
cannot handle it yet;
- Unaligned and/or multidword flat scratch shall work, but it
is legalized now for MUBUF;
- Operand folding cannot optimize FI like with MUBUF yet;
- It will need scaling the value of the SP/FP in the DWARF
expression to recover the unswizzled scratch address;
Differential Revision: https://reviews.llvm.org/D89170
Diffstat (limited to 'llvm/lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions